Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor

ABSTRACT

According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; ifit is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for storing and readingdata in a multilevel nonvolatile memory and to an architecture therefor.

[0003] 2. Description of the Related Art

[0004] According to the most recent market surveys, the most promisingapplications of nonvolatile memories, in particular EPROM and FLASHmemories, in the coming years will mainly regard data storage in thedigital audio/video sector, which is currently undergoing a markedexpansion.

[0005] It is known that the aforesaid applications require increasinglylarge memories, for example to enable storage of several music pieces ona same medium or to increase the photographic quality (for example, byincreasing the number of pixels).

[0006] An important design technique therefor includes the possibilityof programming each memory cell at a level chosen from among a pluralityof levels. At present, the voltage levels usable for programming a cellare binary levels (equal to m, with m=2^(n), where n is the number ofinformation bits that can be stored in the cell). In practice, the lawthat governs multilevel reading and writing is of a binary type, in sofar as memories handle binary data, i.e., at two voltage levels (eitherhigh or low, corresponding, from an electrical standpoint, to groundvoltage and supply voltage).

[0007] Currently memories with two bits per cell, i.e., four-levelmemories, are in an advanced stage of development and enable doubling ofthe capacity of the memory. In addition, memories with an even highernumber of bits per cell, namely with three or even four bits per cell,corresponding to eight and sixteen levels, are under study. For thesememories, above all in the case of sixteen levels, it is very difficultto use the same circuits as for four-level memories; consequently, thetime spent in developing products increases considerably, and theknow-how acquired remains unexploited. In fact, from the standpoints ofthe design and engineering development, multilevel architecture is veryburdensome.

[0008] In order to prevent the need for technical staff to continue todevelop products that involve so much expenditure, it is thereforepreferable to develop architectures that exploit prior know-how to thefull, enabling the design of multilevel memories to advance by shortsteps and departing as little as possible from the prior art.

BRIEF SUMMARY OF THE INVENTION

[0009] An embodiment of the present invention provides a managementmethod and an architecture that allow an increase in the storagecapacity of a nonvolatile memory, without requiring complete re-designof the memory with respect to the prior art. The method for stores datain a multilevel storage device that includes a plurality of memorylocations, each of which can be programmed at a plurality of voltagelevels. The method includes programming each of the memory locations atany of N voltage levels, where N is a non-power of two, depending onwhere a value for storage in the memory location falls among N-1thresholds.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0010] For a better understanding of the present invention, a preferredembodiment thereof is now described, purely by way of non-limitingexample, with reference to the attached drawings, wherein:

[0011]FIGS. 1a and 1 b show the organization of the voltage levels intwo adjacent memory cells in two different cases;

[0012]FIGS. 2a and 2 b show the position of the reference voltages thatcan be used with the organization of the levels illustrated in FIGS. 1aand 1 b;

[0013]FIG. 3 shows a read circuit for pairs of adjacent cells programmedaccording to the organization shown in FIGS. 1a and 1 b and using thereferences of FIGS. 2a and 2 b;

[0014]FIG. 4 shows the waveforms of the timing signals during readingwith the present organization;

[0015]FIG. 5 shows a flow-chart for storing voltage levels in the twocases of FIGS. 1a and 1 b; and

[0016]FIG. 6 is a flow-chart for reading the voltage levels in the twocases illustrated of FIGS. 1a and 1 b.

DETAILED DESCRIPTION OF THE INVENTION

[0017] According to an embodiment of the invention, in each cell of amultilevel memory a non-binary number of levels is stored, inparticular, a number of levels m=(2^(n)+2), for example six, is stored.Since in any case the datum to be supplied to the memory must be of abinary type, an encoding method is provided that enables association ofthe stored non-binary levels to binary codes.

[0018] To this aim, contiguous pairs of cells are associated together,so that they can be read and written simultaneously. In the case,provided by way of example, of storing six levels per cell, which isdescribed hereinafter, without the invention being limited to thespecific case, this corresponds to the possibility of storing twelvedifferent levels, which are the information content of each pair ofcells. Since 12=8+4, this information content corresponds to having 3+2bits, namely, 5 bits every two memory cells. For example, in a 128-Mcellmemory, the binary information content is (5/2)* 128=320 Mbits, insteadof 256 Mbits that may be obtained with a four-level memory (wherein eachcell can be programmed at four different voltage levels).

[0019] With an organization of this sort, the memory cells are read inpairs using read circuits associated to each memory cell and able todiscriminate at least 6 levels. Since the memory cells are read inpairs, a pair of memory cells or adjacent physical cells—hereinafteralso referred to as adjacent memory locations—forms a virtual cell andis addressed by a single address (Ax, Ay).

[0020] In the above situation, according to a possible solution, eachset of five bits to be written or read is broken down into a first setof bits made up of three bits and into a subsequent set of bits made upof two bits. The first set of bits requires eight different levels to bestored. These eight different levels are stored as follows: the firstlocation stores the first six levels, and the second location stores theremaining two levels, which are preferably chosen from between the twohigher levels usable in the second location; the second set of bitsrequires four different levels, which must be stored in a location otherthan that used for the first set of bits.

[0021] Consequently, when the first set of bits encodes one of the firstsix levels of the first set of bits (which, as has been said, can bestored in the first location), the second set of bits can be stored inthe second location. This is the situation shown in FIG. 1a, whichillustrates the six levels usable in the first location and the fourlevels usable in the second location. In this case, the two higherlevels of the second location are “forbidden” levels; i.e., they cannotbe programmed.

[0022] When, instead, the seventh level and the eighth level of thefirst set of bits (which, as has been said, are stored in the secondlocation) are to be stored, the second set of bits cannot be stored inthe second location, and thus the first location is used. This is thesituation shown in FIG. 1b, which illustrates level 7 and level 8 of thefirst set of bits stored in the second location and the four levels ofthe second set of bits stored in the first location. In this case, thefour lower levels of the second location and the two higher levels ofthe first location are “forbidden” levels; i.e., they cannot be used.

[0023] In practice, with the encoding method shown in FIGS. 1a and 1 b,reading of the two higher levels of the second location indicates whichof the following two situations is present: if the last two levels ofthe second location have not been used, this means that reading thefirst location supplies the first set of three bits and reading thesecond location supplies the second set of two bits; if, instead, thetwo higher levels of the second location have been used, this means thatreading the first location supplies the second set of two bits andreading the second location supplies the first set of three bits.

[0024] In either case, the last two levels of the two locations cannotbe used simultaneously.

[0025]FIGS. 2a and 2 b show the arrangement of the reference levels usedfor reading the memory locations in the two cases represented in FIGS.1a and 1 b. As for circuits according to the prior art, fordiscriminating six levels, five references REF1-REF5 are used, which arearranged approximately halfway between pairs of successive levels.

[0026]FIG. 3 shows a block diagram of the circuitry for decoding theinformation contained in two adjacent memory locations, designated by 10a and 10 b, organized in the way described above and belonging to amemory device 5. The circuitry of FIG. 3 implements a parallel sensingwhich, as is known, is the simplest and provides the best performancefrom an electrical standpoint.

[0027] In the diagram of FIG. 3, the memory locations 10 a, 10 b areeach connected to a respective current-to-voltage converter 11 a, 11 bvia an addressing circuit (known and not illustrated). The output of thecurrent-to-voltage converter 11 a is connected to a first input of fivesense amplifiers 12 a 1-12 a 5, which have a second input that receivesone of five references REF1-REF5 via respective current-to-voltageconverters 13 a. Likewise, the output of the current-to-voltageconverter 11 b is connected to a first input of five sense amplifiers 12b 1 -12 b 5, the second input whereof receive one of five referencesREF1 -REF5 via respective current-to-voltage converters 13 b.

[0028] The outputs of the sense amplifiers 12 b 4, 12 b 5 connected tothe second location 10 b and receiving the references REF4 and REF5 areconnected to respective inputs of a NOR gate 15, which iscascade-connected to an inverter 16 supplying a signal en2, of a highlogic level only when at least one of the two sense amplifiers 12 b 4,12 b 5 connected thereto has a high output. In practice, the signal en2is high when the second memory location stores the seventh or the eighthlevel of the first set of bits; otherwise, it is zero. Consequently, itsvalue indicates whether the first set of bits is to be read in the firstmemory location 10 a and the second set of bits is to be read in thesecond memory location 10 b (en2=0), or vice versa (en2=1).

[0029] The outputs of the sense amplifiers 12 a 1-12 a 5 are connectedto a 3-bit encoder 20 via respective CMOS switches 21, controlled by thesignal en2 so as to be closed when en2=0. The outputs of the senseamplifiers 12 b 1 -12 b 5 are connected to the 3-bit encoder 20 viarespective CMOS switches 22, controlled by the signal en2 so as to beclosed when en2=1. Thereby, when en2=0, the 3-bit encoder 20 receivesthe outputs of the sense amplifiers 12 a 1-12 a 5, and when en2=1, the3-bit encoder 20 receives the outputs of the sense amplifiers 12 b 1-12b 5. The 3-bit encoder 20 moreover receives the signal en2 so as todiscriminate the fifth and sixth levels from the seventh and eighthlevels.

[0030] The outputs of the sense amplifiers 12 a 1-12 a 3 are connectedto a 2-bit encoder 23 via respective CMOS switches 24, controlled by thesignal en2 so as to be closed when en2=1. The outputs of the senseamplifiers 12 b 1-12 b 3 are connected to the 2-bit encoder 23 viarespective CMOS switches 25, controlled by the signal en2 so as to beclosed when en2=0. Thereby, when en2=0, the 2-bit encoder 23 receivesthe outputs of the sense amplifiers 12 b 1-12 b 3, and when en2=1, the2-bit encoder 23 receives the outputs of the sense amplifiers 12 a 1-12a 3.

[0031] The 3-bit encoder 20 and the 2-bit encoder 23 are connected torespective output lines 26, along which switches 27 are arranged andcontrolled by the output signals of an address encoder, which in turnreceives three address signals Az(0), Az(1) and Az(2).

[0032] Reading the information contained in the two memory locations 10a, 10 b takes place whenever there is a variation in the addresses {Ax,Ay} (FIG. 4) which causes, in a known way, generation of a pulse of anaddress-transition detection signal ATD (not shown), which in turngenerates all the read sync signals known to the persons skilled in theart. Consequently, the contents of the two memory locations 10 a, 10 baddressed are read and encoded by the circuitry of FIG. 3, taking thevalues of the first set of bits and of the second set of bits in the waypreviously described. The bits thus encoded are outputted sequentiallyusing an appropriate combination of addresses {Az_(n)}, as shown in thetiming of FIG. 4.

[0033] The essential operations for writing and reading a virtual cellof address (Ax, Ay) are shown in FIGS. 5 and 6.

[0034] According to FIG. 5, which regards writing, initially a set ofbits that are to be stored is divided into two or more sets, step 30.Then, the virtual cell of address (Ax, Ay) is addressed, step 31. It isverified whether the first set of bits (in the example considered above,three bits) encodes a number higher than the number of levels that canbe stored in a single location (in the example, whether level 7 or level8 is to be stored), step 32. If not, the first set of bits is stored ina first location (in the example, in the first memory location 10 a);i.e., the first location is programmed at a level corresponding to thevalue encoded by the first set of bits, step 33, and the second set ofbits is stored in a second location (in the example shown, in the secondmemory location 10 b); i.e., the second location is programmed at alevel given by the value encoded by the second set of bits, step 34. Inthe affirmative, the first set of bits is stored in the second location,step 35, and the second set of bits is stored in the first location(programming of the first location at the value encoded by the secondset of bits), step 36.

[0035] According to FIG. 6 and to what explained for the circuit of FIG.3, during reading, first the virtual cell of address (Ax, Ay) isaddressed, step 40. Then the cell is read, step 41. It is verifiedwhether one of the levels of the second location reserved to the firstset of bits has been written (in the example, whether level 5 and/orlevel 6 of the second memory location 10 b has been written), step 42.If not, the read circuits of the first location are connected to theencoder of the first set of bits (in the example shown, to the 3-bitencoder 20), step 43, and the read circuits of the second location areconnected to the encoder of the second set of bits (in the example tothe 2-bit encoder 23), step 44. In the affirmative, the read circuits ofthe first location are connected to the encoder of the second set ofbits, step 45, and the read circuits of the second location areconnected to the encoder of the first set of bits, step 46.

[0036] The solution described herein affords the important advantage ofimplementing a non-binary architecture for reading the informationstored in nonvolatile memory cells, with minimal overall dimensions anda minimal logic complexity, exploiting known multilevel techniques.

[0037] Finally, it is clear that numerous modifications and variationsmay be made to the method and memory described and illustrated herein,all falling within the scope of the invention, as defined in theattached claims. In particular, the same architecture may be applied forstoring any non-binary number of levels in each memory location. Thechoice of the particular location to be used for storing each set ofbits is arbitrary. The levels associated to each set of bits can bechosen in a way different from the one illustrated. The levels encodedby the first set of bits and stored in the second memory location may beother than the ones illustrated (for instance, the second memorylocation 10 b could store levels 1 and 2, instead of 7 and 8, of thefirst set of bits; in this case, the first memory location should storelevels 3-8 of the first set of bits). Finally, reading may be performedvia a different type of multilevel sensing, such as merely serial,dichotomous, mixed parallel-serial sensing, etc.. Furthermore, from atheoretical standpoint it is possible to store more than two sets ofbits in more than two adjacent memory locations.

[0038] All of the above U.S. patents, U.S. patent applicationpublications, U.S. patent applications, foreign patents, foreign patentapplications and non-patent publications referred to in thisspecification and/or listed in the Application Data Sheet, areincorporated herein by reference, in their entirety.

1. A method for storing data in a multilevel nonvolatile storage devicecomprising a plurality of memory locations, each of which can beprogrammed at a plurality of voltage levels, the method comprising:programming each of the memory locations at any of N voltage levels,where N is a non-power of two, depending on where a value for storage inthe memory location falls among N-1 thresholds.
 2. The data-storagemethod according to claim 1, wherein N is 2^(n)+2 and n≧2.
 3. Thedata-storage method according to claim 2, wherein N is six.
 4. Thedata-storage method according to claim 1, wherein an integer number ofbits is stored in at least two memory locations.
 5. The data-storagemethod according to claim 4, comprising the steps of: a) dividing saidinteger number of bits into at least two sets of bits, wherein at leastone first set of bits defines a binary number of levels that is greaterthan said non-binary number; b) checking whether said first set of bitsencodes a value to be stored in a first of said memory locations; c1) incase of a positive outcome of step b), storing said first set of bits insaid first memory location and storing a second set of bits in a secondof said memory locations; c2) in case of a negative outcome of step b),storing said first set of bits in said second memory location andstoring a second set of bits in said first memory location.
 6. Thedata-storage method according to claim 5, wherein said step c1)comprises storing said second set of bits in a first sub-set of levelsof said second memory location; and said step c2) comprises storing saidfirst set of bits in a second sub-set of levels of said second memorylocation, said second subset of levels being separate from said firstsubset of levels.
 7. The data-storage method according to claim 6,comprising the steps of: d) reading said first and second memorylocations; e) checking whether one of the levels of said second subsetof levels of said memory location has been written; f1) in case of apositive outcome, assigning said level of said second sub-set of levelsto said first set of bits, and assigning a level read in said firstmemory location to said second set of bits; f2) in case of a negativeoutcome, assigning a level read in said first memory location to saidfirst set of bits, and assigning a level read in said second memorylocation to said second set of bits.
 8. A multilevel nonvolatile memorydevice comprising a plurality of memory cells, each memory cellincluding a pair of memory locations that together store an odd numberof bits.
 9. The nonvolatile memory device according to claim 8, furthercomprising: a first set of sense amplifiers coupled to a first memorylocation of a selected one of the memory cells; a second set of senseamplifiers coupled to a second memory location of the selected memorycell; a first encoder that encodes voltage levels of the memory cellsinto bit values; and a routing circuit structured to alternatelyelectrically connect the first encoder to the first set of senseamplifiers or the second set of sense amplifiers depending on a value ofa voltage level stored in the first memory location of the selectedmemory cell.
 10. The non-volatile memory device according to claim 9,further comprising a second encoder that encodes voltage levels of thememory cells into bit values, wherein the routing circuit is structuredto alternately electrically connect the second encoder to the second setof sense amplifiers or the first set of sense amplifiers depending onthe value of the voltage level stored in the first memory location ofthe selected memory cell.
 11. The nonvolatile memory device according toclaim 8, wherein each said memory cell is addressed by a single address.12. The nonvolatile memory device according to claim 8, wherein saidmemory locations of each memory cell are adjacent.
 13. The nonvolatilememory device according to claim 8, further comprising: means fordividing said odd number of bits of a selected one of the memory cellsinto first and second sets of bits; first checking means checkingwhether said first set of bits encodes a value to be stored in a firstof said memory locations of the selected memory cell, said firstchecking means generating storage information having a first value and asecond value; first programming means for writing said first set of bitsin said first memory location and the second set of bits in a second ofsaid memory locations of the selected memory cell, said firstprogramming means being activated in presence of said first value ofsaid storage information; and second programming means for writing saidfirst set of bits in said second memory location and the second set ofbits in said first memory location, said second programming means beingactivated in presence of said second value of said storage information.14. The nonvolatile memory device according to 13, wherein said firstprogramming means comprise first writing means for writing said secondset of bits in a first sub-set of levels of said second memory location,said first writing means being activated in presence of said first valueof said storage information; and said second programming means comprisesecond writing means for storing said first set of bits in a secondsub-set of levels of said second memory location, said second sub-set oflevels being separate from said first sub-set of levels, said secondwriting means being activated in presence of said second value of saidstorage information.
 15. The nonvolatile memory device according toclaim 14, comprising: a first read circuit associated with said firstmemory location; a second read circuit associated with said secondmemory location; second checking means for checking whether one of thelevels of said second sub-set of levels of said second memory locationhas been written, said second checking means generating a level-checksignal having a first value and a second value; a first encoder for saidfirst set of bits; a second encoder for said second set of bits; firstrouting means connecting said first read circuit to said first encoderin presence of said first value of said level-check signal, andconnecting said first read circuit to said second encoder in presence ofsaid second value of said level-check signal; and second routing meansconnecting said second read circuit to said second encoder in presenceof said first value of said level-check signal, and connecting saidsecond read circuit to said first encoder in presence of said secondvalue of said level-check signal.
 16. A method of storing a group ofbits into first and second memory locations, comprising: dividing thegroup of bits into first and second sets of bits; storing the second setin the second memory location if a value of the bits of the first set isless than a reference value; and storing the second set in the firstmemory location if the value of the bits of the first set is not lessthan the reference value.
 17. The method of claim 16, furthercomprising: storing the first set in the first memory location if thevalue of the bits of the first set is less than the reference value; andstoring the first set in the second memory location if the value of thebits of the first set is not less than the reference value.
 18. Themethod of claim 16 wherein one of the first and second sets consists ofan odd number of bits and another of first and second sets consists ofan even number of bits.
 19. A method of reading a memory cell thatincludes first and second memory locations, comprising: determinewhether the second memory location stores a predetermined voltage levelindicating that the first memory location stores a first set of bits andthe second memory location stores a second set of bits; if the secondmemory location stores the predetermined voltage level, thenelectrically connecting the first memory location to a first bitencoder; and if the second memory location does not store thepredetermined voltage level, then electrically connecting the secondmemory location to the first bit encoder.
 20. The method of claim 19,further comprising: if the second memory location stores thepredetermined voltage level, then electrically connecting the secondmemory location to a second bit encoder; and if the second memorylocation does not store the predetermined voltage level, thenelectrically connecting the first memory location to the second bitencoder.
 21. A multilevel nonvolatile memory device comprising: aplurality of memory locations structured to store respective voltagevalues; and a write circuit coupled to the memory locations andstructured to program the memory locations with the respective voltagevalues within N predetermined ranges, where N is a non-power of two. 22.The nonvolatile memory device according to claim 21,wherein pairs of thememory locations are associated together and form a plurality of virtualmemory cells, each said memory cell being addressed by a single address.23. The nonvolatile memory device according to claim 22, wherein saidmemory locations of each memory cell are adjacent.
 24. The nonvolatilememory device according to claim 22, further comprising: means fordividing an integer number of bits, to be stored in a selected one ofthe memory cells, into first and second sets of bits, wherein the firstset of bits is an integer number greater than N; first checking meanschecking whether said first set of bits encodes a value to be stored ina first of said memory locations of the selected memory cell, said firstchecking means generating storage information having a first value and asecond value; first programming means for writing said first set of bitsin said first memory location and the second set of bits in a second ofsaid memory locations of the selected memory cell, said firstprogramming means being activated in presence of said first value ofsaid storage information; and second programming means for writing saidfirst set of bits in said second memory location and the second set ofbits in said first memory location, said second programming means beingactivated in presence of said second value of said storage information.25. The nonvolatile memory device according to 24, wherein said firstprogramming means comprise first writing means for writing said secondset of bits in a first sub-set of levels of said second memory location,said first writing means being activated in presence of said first valueof said storage information; and said second programming means comprisesecond writing means for storing said first set of bits in a secondsub-set of levels of said second memory location, said second sub-set oflevels being separate from said first sub-set of levels, said secondwriting means being activated in presence of said second value of saidstorage information.
 26. The nonvolatile memory device according toclaim 25, comprising: a first read circuit associated with said firstmemory location; a second read circuit associated with said secondmemory location; second checking means for checking whether one of thelevels of said second sub-set of levels of said second memory locationhas been written, said second checking means generating a level-checksignal having a first value and a second value; a first encoder for saidfirst set of bits; a second encoder for said second set of bits; firstrouting means connecting said first read circuit to said first encoderin presence of said first value of said level-check signal, andconnecting said first read circuit to said second encoder in presence ofsaid second value of said level-check signal; and second routing meansconnecting said second read circuit to said second encoder in presenceof said first value of said level-check signal, and connecting saidsecond read circuit to said first encoder in presence of said secondvalue of said level-check signal.